Cadence Design Systems announced Cadence System-Level Verification IP (System VIP), a new suite of tools and libraries for automating system-on-chip (SoC) testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis.
Using Cadence System VIP, customers creating complex hyperscale, automotive, mobile and consumer chips can improve chip-level verification efficiency by up to 10X.
The new Cadence System VIP solution takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. Tests created using the Cadence System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to post-silicon bring-up.
Cadence System VIP consists of four new tools and libraries:
- System testbench generator: Allows users to automatically generate SoC testbenches with complex memory, cache, interface and bus configurations
- System traffic libraries: Provide users with a rich portfolio of pre-defined tests that can be plugged into a System VIP testbench, including coherency, performance, PCI Express (PCIe) and NVMe subsystems
- System performance analyzer: Offers comprehensive performance analysis reporting and visualization for memory subsystems, interconnects and peripherals
- System verification scoreboard: Provides comprehensive data and cache-coherency checks across coherent interconnects, memories and peripherals
“Renesas has used Cadence VIP for many years and values Cadence’s leadership in advanced SoC verification technologies,” said Tetsuya Asano, director, Design Methodology Department, Shared R&D EDA Division at Renesas.
“By adding the new System VIP to our existing verification environment based on the Cadence Xcelium and Palladium platforms, and improving stimulus re-use and automation, we’ve further accelerated the SoC verification process with 10X more efficiency, enabling us to deliver innovative, high-quality products to our customers faster.”
“Through our collaboration with Cadence, we’ve reduced some of the complex SoC verification challenges, especially around I/O peripherals,” said Tran Nguyen, director of Design Services at Arm.
“By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”
“Verification challenges increase exponentially as the number and complexity of integrated IP blocks on an SoC grow,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence.
“Our new Cadence System VIP solution dramatically improves verification throughput by automating some of today’s most critical labor-intensive chip-level verification challenges.”
The Cadence System VIP tool suite is part of the broader Cadence Verification Suite and supports the company’s Intelligent System Design strategy. The Cadence Verification Suite is comprised of core engines and smart verification technologies that increase verification throughput and design quality, fulfilling verification requirements for a wide variety of applications and vertical segments.