Cadence Design Systems announced Xcelium Apps, a portfolio of domain-specific technologies implemented natively on the Cadence Xcelium Logic Simulator kernel that enable automotive, mobile and hyperscale design teams to achieve the highest verification performance.
By mixing and matching Xcelium Apps, customers can achieve up to a 10X regression throughput improvement.
The Xcelium Apps portfolio includes:
- Machine Learning: The Xcelium Machine Learning (ML) App utilizes proprietary ML technology to reduce regression times by learning from previous regression runs and guiding the Xcelium randomization kernel to either achieve the same coverage with significantly less simulation cycles or catch more bugs around specific coverage points of interest.
- Mixed-Signal: The Xcelium Digital Mixed-Signal (DMS) App enables native co-simulation with Cadence Spectre SPICE analog simulation, as well as advanced SystemVerilog real number model-based simulation.
- Multi-Core: The Xcelium Multi-Core (MC) App significantly reduces runtime for long-running high-activity tests by multi-threading the Xcelium kernel, such as on gate-level design for test (DFT) simulations.
- Safety: The Xcelium Safety App enables serial and concurrent fault simulation, which when combined with the Cadence safety verification full flow comprised of Jasper Safety, vManager Safety, and Midas Safety Planner, enables the highest performance safety campaign execution for ISO 26262 compliance.
- Power Playback: The Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms captured by Palladium emulation onto a timing-annotated gate-level netlist for glitch-accurate power estimation of multi-billion gate SoC designs.
- X-Pessimism Removal: The Xcelium X-Pessimism Removal (XPR) App shortens debug time by using advanced algorithms to make the propagation of “X” values in simulation more accurate.
Xcelium Apps are the next step in the evolution of logic simulation performance,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “These apps deliver domain-specific technologies to enable the highest levels of verification performance at both the IP and full-chip level of modern SoC designs.”
The Xcelium Apps and the Xcelium Logic Simulator are part of the Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio, the vManager Verification Management Platform, memory and interface Verification IP (VIP), and System VIP.
“Alif Semiconductor uses Cadence’s Xcelium Logic Simulator as part of our verification flow for our advanced AI/ML and IoT designs, helping accelerate our simulation tasks. We also utilize the Xcelium DMS app to verify our mixed-signal designs along with the base simulator. With the Xcelium simulator, we can achieve verification closure and meet our time-to-market goals,” said Edward Youssoufian, Vice President of Engineering, Alif Semiconductor.
“We have extensive experience using Cadence’s Xcelium Logic Simulator to verify our designs. The new Xcelium Apps are a useful extension of the simulator, providing us the flexibility to deploy advanced technologies natively on the Xcelium engine as and when we need them. Our automotive chips must adhere to the ISO 26262 standard, and the Xcelium Safety App has helped us ensure compliance and identify complex bugs using state-of-the-art verification techniques,” said Yi Gu, SoC Design Director, AutoChips.
“Cadence’s new Xcelium PowerPlayback App is helping our team accurately calculate power consumption in the early stages of the design cycle. The introduction of Xcelium Apps, including the Xcelium PowerPlayback App, allows us to tailor the Xcelium Logic Simulator to match our verification demands, ensuring we have the correct functionality and can meet our aggressive time-to-market goals,” said Yee-Wei Huang, Vice President and Spokesman, Realtek.
“By incorporating the Cadence Xcelium Machine Learning App as part of our verification flow, we were able to accelerate coverage convergence with fewer regression tests. This helps us meet our aggressive deadlines while maximizing verification performance and overall verification efficiency,” said Tatsuya Kamei, Distinguished Engineer, Automotive SoC Business Division, Renesas Electronics.
“Our team has extensive experience utilizing Cadence’s Xcelium Logic Simulation to address our verification needs, and the new Xcelium Apps extend the platform’s capabilities even further. The Xcelium Multi-Core App allows us to shorten long-running DFT pattern simulations using multiple cores. These Xcelium Apps enable timely validation closure, and we plan to use them in our verification flow moving forward,” said Roberto Mattiuzzo, Design Manager, Microcontrollers & Digital ICs Group, RF & Communication Division, STMicroelectronics.