RISC-V Soft CPU Contest challenges designers to develop a hardware secure RISC-V soft CPU solution

The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), announced the call for submissions for the RISC-V Soft CPU Contest.

The aim of the contest is to challenge designers to develop a hardware secure RISC-V soft CPU solution that can thwart malicious software security attacks. The contest is sponsored by RISC-V Foundation members Microchip Technology Inc. and Thales.

“With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an incredible opportunity for the ecosystem to collaborate to develop more robust solutions for the growing security demands of today and the future,” said Calista Redmond, CEO of the RISC-V Foundation.

“This contest is an opportunity for designers and hardware enthusiasts to rethink what is possible with computing design and build a secure RISC-V soft CPU that can prevent software security attacks.”

The contest targets the Creative Development Board using Microchip’s 25K LUT IGLOO 2 FPGA available at Future Electronics for $149.95.

Thales will evaluate the nominations and select the top three winners overall. Judges will review how many of the five security attacks are thwarted, in addition to evaluating the total resources used, including logic elements, math blocks and internal RAM, as well as CPU core FMAX, expected power consumption and the amount of changes to the compiler.

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RISC-V Soft CPU Contest challenges designers to develop a hardware secure RISC-V soft CPU solution